(1) Field of the Invention
The invention relates to a method of controlling the critical dimension width of polysilicon, and more particularly, to a method of controlling the critical dimension width of polysilicon by planarizing the photoresist underlayer using a spin-on-glass layer in the manufacture of integrated circuits.
(2) Description of the Prior Art
Referring to FIG. 1, there is shown a portion of a partially completed integrated circuit in which there is a silicon substrate 10. Field oxide regions 12 are formed in and on the silicon substrate resulting in a uneven topography of the top surface of the substrate. A layer 14 of polysilicon is deposited over the surface of the substrate. A layer of photoresist 16 coats the surface of the polysilicon layer 14 and planarizes the substrate. The differing photoresist depths A and B will make an imperfect image and resulting mask.
FIG. 2 shows a top view of the active area 20 of the semiconductor substrate. Field oxide regions 12 surround the active area. This figure illustrates the necking problem 17 of the PRIOR ART in polysilicon region 14, especially for areas having a large change in topography such as the field oxide to active areas. The differing photoresist thicknesses cause the different critical dimension width of the polysilicon due to the standing-wave effect. This necking problem could result in early breakdown of the integrated circuit via the neck, 17. The circuit critical dimension (CCD), Testline, and Testkey can differ by as much as 0.15 micrometers. Testline and testkey are process monitor patterns having the same dimension as the CCD, but different surrounding patterns.
U.S. Pat. Nos. 5,003,062 to Yen and 4,775,550 to Chu et al describe processes for planarization using spin-on-glass materials. These Patents are cited to show the general use of spin-on glass materials in the art.